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Design of Analog CMOS Integrated Circuits; Mc-Graw Hill Inc.: New York, NY, USA, 2015. [Google Scholar]Hesham, O. Fast and accurate technique for comparator offset voltage simulation. Microelectron. J. 2019, 89, 91–97. [Google Scholar]Peng, X.; Gao, A.; Chen, Z.; Zhang, H.; Li, Y.; Cao, W.; Liu, X.; Tang, H. A Novel Comparator Offset Calibration Technique for SAR ADCs. In Proceedings of the 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, China, 6–8 June 2018. [Google Scholar]Zhang, Y.; Cai, J.; Li, X.; Zhang, Y.; Su, B. A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration. Microelectron. J. 2021, 116, 105–244. [Google Scholar] [CrossRef] Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 2. The common-mode buffer. Figure 2. The common-mode buffer. Figure 3. The symmetrical OTA. Figure 3. The symmetrical OTA. Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 6. Differential preamplifier with offset voltage. Figure 6. Differential preamplifier with offset voltage. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 8. Control logic circuit. Figure 8. Control logic circuit. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 10. The timing diagram of comparator offset trimming. Figure 10. The timing diagram of comparator offset trimming. Figure 11. The layout of the comparator. Figure 11. The layout of the comparator. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 13. Transient simulation test bench of the proposed comparator. Figure 13. Transient simulation test bench of the proposed comparator. Figure 14. Transient simulation curves of the proposed comparator (ripple = 30 μV). Figure 14. Transient simulation curves of

1. IntroductionSuccessive approximation register analog-to-digital converters (SAR ADCs) are widely used in sensing detection, industrial control, and other fields because of their simple structure and low power consumption [1]. The comparator, as the core component of analog-to-digital conversion in SAR ADC, has a very important impact on the speed, accuracy, and power consumption of SAR ADC. Comparators can be separated into two main categories: the static topology working continuously and the dynamic topology making a decision after being initiated with a clock signal [2,3]. In recent years, dynamic comparators have been widely used because of their advantages of zero static power consumption, high speed, and rail-to-rail output. The dynamic comparator with low offset SR latch reported in [4] can work up to 100 MHz clock frequency while the average dynamic power and standard deviation in offset voltage are 18 µW and 3.06 mV, respectively. In [5], a dynamic latch comparator with fast response and low kickback noise was designed in a 10-bit synchronous SAR ADC; the metastable state was avoided by the effectively increased headroom for comparator to reduce the data bit error rate (BER). In [6], a regenerative feedback dynamic latch comparator was presented in a microdevice composed of a 4 × 4 array of photodiodes and readout circuits. The two cross-coupled pairs of the latch were switched through their drains to eliminate backgating effects and promote faster regeneration. The dynamic proximity comparator designed in [7] utilized latches with positive feedback at the second stage to generate rail-to-rail digital outputs. In comparison, a static comparator has high precision and low offset voltage, but it has high power consumption and low speed. A dynamic comparator has low power consumption and high speed, but its offset voltage and noise performance are relatively poor. In both the static and dynamic comparators, there are some nonidealities such as device mismatch and noise. These nonidealities will cause the offset voltage of the comparator, which will lead to decreased accuracy of the comparator. To improve the accuracy of comparators, offset cancellation techniques are usually adopted.The conventional offset calibration techniques for comparators mainly include correlated double sampling (CDS), autozeroing, and chopper stabilization techniques [8,9]. In order to improve the speed of a comparator while ensuring accuracy, a multi-stage cascade structure is often adopted in the comparator. The most common offset cancellation techniques in these multi-stage comparators are based on using preamplifiers with input/output offset storage (IOS/OOS)

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Self-calibration operation is performed only when the chip is first powered on, so it does not affect the conversion time of the ADC during normal operation of the ADC. 4.2. Implementation and Measurement of the Proposed ComparatorTwo 12-bit SAR ADCs with and without a self-calibrated comparator were integrated into the two same-type MCU chips for testing, respectively. An MCU chip with the self-calibration comparator is named PT101CC, and another MCU chip without the self-calibration comparator is named PT101CB. Figure 18 shows the PT101CC and the printed circuit board (PCB) used for testing, and Figure 19 shows the PT101CB test environment.After the obtained test data are analyzed and processed by computer software, the output waveforms of the two 12-bit SAR ADCs in the PT101CB and the PT101CC were obtained and are shown in Figure 20a,b respectively. “o” and “+” represent the measured output signal and the ideal output signal of the two 12-bit SAR ADCs, respectively. Figure 20 shows that when Vin = 0 V, the output of the PT101CB is code = 2, while the output of the PT101CC is code = 0. The minimum voltage detected by the ADC based on the proposed comparator with the self-calibration is 0 LSB, and the offset voltage can be eliminated effectively.The output spectrum of the Nyquist frequency fast Fourier transform (FFT) spectrum for the 12-bit SAR ADC with and without calibration is shown in Figure 21. The improved ENOB and signal-to-noise plus distortion ratio (SNDR) are 11.33 bits and 70.00 dB, respectively, in Figure 21a with calibration, while the ENOB and SNDR are 10.68 bits and 66.08 dB, respectively, in Figure 21b without calibration. The ENOB and SNDR with calibration are increased by 0.65 bits and 3.92 dB, respectively.The performance parameters of the proposed comparator with self-calibration designed in this study are compared with those of other similar comparators in Table 2. The proposed comparator improves the speed and accuracy of the comparator at the cost of the overall power consumption and meets the high-precision and high-speed requirements of touch MCU applications. The supplied voltage of the proposed comparator is 5 V, which is higher than that of other comparators, mainly to meet the requirement of a 5 V supply voltage for a touch MCU chip. Therefore, compared with the SAR ADCs in other studies, the power consumption of the designed SAR ADC is significantly increased, and the obtained figure of merit