Download clock doubler with delay line

Author: c | 2025-04-23

Download Clock-doubler with delay line - Clock-doubler circuit simulation built in Java . Clock-doubler with delay line DOWNLOAD NOW 511 downloads so far. app Clock-doubler with delay line original extension iphone official download format app Clock-doubler with delay line 1.0 torrent index torrent index stable stable Clock-doubler with delay line 1.0 10.11.4 dutch download open.torrent Clock-doubler. with,delay line 1.0 ; isoHunt. download-from proxy stable crack.

Clock-doubler with delay line

Inverter 256, the output of which is connected to the gate electrode of transistor 254. the clock signal CLKBP is also apphed to the input of another inverter 260, the output of which is connected to the gate electrode of an n-channel transistor 262. the drain of transistor 262 is connected to central node 230. the source of transistor 262 is selectively coupled to VSS via either of n-channel transistors 264 or 266. the gate electrode of transistor 264 is connected to the delayed clock signal CLKDLYB from the clock control circuit 16. a NOR gate 268 receives the high timing signal HTIME at one input and receives the clock timing modification signal CLKTMB via line 222 at a second input. the output of gate 268 is connected to the gate electrode of transistor 266. clock selector circuitry 18 depends on the status of the signal CLKTMB, which is the control signal programmed by the mode registers. CLKTMB the control signal programmed by the mode registers. the timing signal HTIME arrives and causes the signal DCLKB to be generated. DCLKB will also go high and it will stay high for however long the HTIME one-shot lasts. Consequently, this part of the signal DLCLKB is essentially the same as the HTIME signal. the low timing signal LTTME for which, unlike HTIME, the time delay is not programmed by the signal CLl, provides a fixed one-shot delay. the HTIME signal In the clock doubler mode, the HTIME signal provides a high pulse and then goes low, and then the LTIME signal provides a further pulse. If the clock doubler mode is not active, then the HTIME signal simply provides the high pulse and times out. the riming signal CLKTMB For the clock doubler mode, the riming signal CLKTMB must be on (low level) and CLl must be off (low level) in order for L ⁇ ME to provide another high pulse during the same external clock cycle. the HTTME signal In the normal mode of operation, the HTTME signal will determine the high time of the output signal DCLKB, and it will time out without anything else happening. the signal output is desired to be very fast because a signal was intercepted from the input buffer. It is modified and put back into the input buffer circuit as DCLKB, and the circuitry is desired to result in minimum skews. It takes time to generate the signals HTTME and LTTME. If the circuit relied simply on HTIME, it would not provide a signal fast enough and would result in additional skew and delay. this embodiment uses a feed forward approach so that when the clock fires (CLKBP changes states), it immediately (or very

Clock-doubler with delay line - Download

Connected to the gate electrode of a p-channel transistor 246. A further transistor 248 is connected in series with transistor 246 so that the source-drain paths thereof selectively connect node 230 to VCC. The gate electrode of p-channel transistor 248 is connected to the output of an inverter 250. Inverter 250 inverts the inverted clock signal CLKBP from the clock buffer circuit 14. A fifth path to a power supply voltage (VSS) is provided. The inverted clock timing signal CLKBP is apphed to the gate electrode of an n-channel transistor 252 which is connected in series with another n-channel transistor 254. The source-drain paths of transistor 252, 254 selectively connect node 230 to VSS. The low timing signal LTIME from the clock one-shot circuits 20 is inverted by an inverter 256, the output of which is connected to the gate electrode of transistor 254. Sixth and seventh paths from node 230 to a power supply are provided. The clock signal CLKBP is also apphed to the input of another inverter 260, the output of which is connected to the gate electrode of an n-channel transistor 262. The drain of transistor 262 is connected to central node 230. The source of transistor 262 is selectively coupled to VSS via either of n-channel transistors 264 or 266. The gate electrode of transistor 264 is connected to the delayed clock signal CLKDLYB from the clock control circuit 16. A NOR gate 268 receives the high timing signal HTIME at one input and receives the clock timing modification signal CLKTMB via line 222 at a second input. The output of gate 268 is connected to the gate electrode of transistor 266. It will be appreciated that the operation of clock selector circuitry 18 depends on the status of the signal CLKTMB, which is the control signal programmed by the mode registers. In general, the timing signal HTIME arrives and causes the signal DCLKB to be generated. When HTIME goes high, DCLKB will also go high and it will stay high for however long the HTIME one-shot lasts. Consequently, this part of the signal DLCLKB is essentially the same as the HTIME signal. When the clock signal goes in the other direction, however, the low timing signal LTTME, for which, unlike HTIME, the time delay is not programmed by the signal CLl, provides a fixed one-shot delay. In the clock doubler mode, the HTIME signal provides a high pulse and then goes low, and then the LTIME signal provides a further pulse. If the clock doubler mode is not active, then the HTIME signal simply provides the high pulse and times out. For the clock doubler mode, the riming signal CLKTMB must be on (low

Clock-doubler with delay line - Bitbucket

* 1993-04-02 1994-11-09 Nec Corporation Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals EP0640986A1 (en) * 1993-08-26 1995-03-01 Siemens Aktiengesellschaft Semiconductor memory device and method for testing the same Cited By (7) * Cited by examiner, † Cited by third party Publication number Priority date Publication date Assignee Title US7260020B2 (en) 2002-03-19 2007-08-21 Broadcom Corporation Synchronous global controller for enhanced pipelining US8693279B2 (en) 2002-03-19 2014-04-08 Broadcom Corporation Synchronous global controller for enhanced pipelining US9159385B2 (en) 2002-03-19 2015-10-13 Broadcom Corporation Memory architecture with local and global control circuitry US9542997B2 (en) 2002-03-19 2017-01-10 Broadcom Corporation Memory architecture with local and global control circuitry EP1376596A2 (en) * 2002-06-21 2004-01-02 Broadcom Corporation Synchronous global controller for enhanced pipeline EP1585137A1 (en) * 2002-06-21 2005-10-12 Broadcom Corporation Synchronous global controller for enhanced pipelining EP1376596B1 (en) * 2002-06-21 2008-01-09 Broadcom Corporation Synchronous global controller for enhanced pipeline Similar Documents Publication Publication Date Title US6894547B2 (en) 2005-05-17 Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit US6081462A (en) 2000-06-27 Adjustable delay circuit for setting the speed grade of a semiconductor device US20050104640A1 (en) 2005-05-19 Apparatus and method for duty cycle correction DE19503390C2 (en) 1997-02-27 Data output buffer control circuit US20020050847A1 (en) 2002-05-02 Semiconductor device with dummy interface circuit JP3917217B2 (en) 2007-05-23 Initialization circuit for semiconductor memory device US6339353B1 (en) 2002-01-15 Input circuit of a memory having a lower current dissipation JPH1079191A (en) 1998-03-24 Internal step-up-voltage generator for semiconductor storage device US6333875B1 (en) 2001-12-25 Semiconductor circuit with adjustment of double data rate data latch timings US6023181A (en) 2000-02-08 High speed unitransition input buffer KR100425446B1 (en) 2004-03-30 A input circuit of semiconductor memory device including clock selection circuit for selecting predetermined clock signal to be calibrated and the method thereof US6239642B1 (en) 2001-05-29 Integrated circuits with variable signal line loading circuits and methods of operation thereof KR100581444B1 (en) 2006-07-25 Apparatus for controlling circuit response during power-up WO1998036417A1 (en) 1998-08-20 Clock doubler and minimum duty cycle generator for sdrams US5982188A (en) 1999-11-09 Test mode control circuit of an integrated circuit device KR100267088B1 (en) 2000-10-02 Reference voltage generator of a semiconductor memory device KR0167680B1 (en) 1999-02-01 Internal power supply voltage generation circuit of semiconductor memory device JPH0758887B2 (en) 1995-06-21 Variable clock delay circuit using RC time constant KR0119886B1 (en) 1997-10-17 Mode setting circuit of semiconductor memory device and method thereof US5550500A (en) 1996-08-27 Timing delay modulation scheme for integrated circuits JP3434741B2 (en) 2003-08-11 Semiconductor storage device US6868018B2 (en) 2005-03-15 Memory circuit, method for manufacturing and method for operating the same KR100596852B1 (en) 2006-07-04 Internal Clock Signal Generator KR100213222B1 (en) 1999-08-02 Row Address Signal Control Circuit of Semiconductor Memory Device KR100308071B1 (en) 2001-10-19 Precharge Device. Download Clock-doubler with delay line - Clock-doubler circuit simulation built in Java . Clock-doubler with delay line DOWNLOAD NOW 511 downloads so far. app Clock-doubler with delay line original extension iphone official download format app Clock-doubler with delay line 1.0 torrent index torrent index stable stable Clock-doubler with delay line 1.0 10.11.4 dutch download open.torrent Clock-doubler. with,delay line 1.0 ; isoHunt. download-from proxy stable crack.

Clock-doubler with delay line - uni-hamburg.de

Which is connected to the drain of n-channel transistor 288, the source of which is connected to ground. Transistor 286 has a gate electrode connected to the output of inverter 284 (the HTIME signal), and transistor 288 ⁇ has a gate electrode coupled to receive the' high time enabling signal HTEN. Circuitry for providing the low timing signal LTTME is very similar and includes a constant current source formed around transistors 290-295. the output of that constant current source appears on a conductive line 291 which is connected to one side of transistors functioning as capacitors 296, the other sides of which are connected to VSS. Conductive line 291 is applied to the input of an inverter 297, and line 291 is connected selectively to ground via the source-drain paths of series-connected transistors 298 and 299. the output of inverter 297 provides the low timing signal LTIME, which is also connected to the gate electrode of transistor 298. the gate electrode of transistor 299 is connected to receive the low timing enabling signal LTEN. the first constant current source of circuit 20 includes transistor 272 which turns on and off under control of the mode register signal CLl. When transistor 272 is conductive, it reduces the resistance between transistors the low time enable signal LTEN is kept high when the circuitry is not in the clock doubler test mode. With LTEN high, transistor 290 is kept off. Accordingly, the low riming signal LTTME, which is provided to the clock selector circuitry, is used only when the clock doubler mode is enabled. the invention addresses the problem of duty cycles different than 50% in the external clock signal by modifying the internal clock high time, using a precision delay time which is triggered by the rising edge of the external clock. Furthermore, the high pulse generated, under "normal operation" (non-doubler mode), modifies the pulse width differently for different /CAS latencies (our implementation programs the same pulse duration for /CAS latencies of 2 and 3, but changes the pulse duration for /CAS latency of 1. the invention includes programming different internal pulse widths for all possible /CAS latencies. If the mode register signal CLl is high, then the voltage at the gate electrode of transistor 272 will be low, and that transistor will be nonconductive. HTIME is shorter in duration. the generation of the other timing signal LTTME is similar, but it is not modified on the basis of the status of the CLl signal. However, in a variation of the preferred embodiment, a similar change in the current can be achieved by adding a transistor and/or further resistances between transistors 292 and 295. Fig. 7 shows the circuitry leading to the

Clock-doubler with delay line - Download, Screenshots - Softpedia

Is limited when the external clock signal has a duty cycle other than 50%, i.e. when the external clock signal is in the high state for a high percentage of the clock cycle time or when the external clock signal is in the high state for a low percentage of the clock cycle time. Disclosure of Invention To overcome the aforementioned problems, a technique is used where an internal clock or timer provides a clock or timing signal so that the minimum internal requirement for the internal clock high time is satisfied. This minimum time permits acceptable internal clock low durations with all expected external clock frequencies. However to ensure that optimal internal clock timing exists for all anticipated frequencies, the timing is preferably programmable. In a preferred form, the "CAS latency" is user programmable to alter the internal pulse width. Preferably, the internal timing circuit includes at least one, and preferably two, timers, e.g. one-shot circuits. Moreover, a clock doubler circuit is incorporated as part of the circuit and method. This clock doubler allows the external clock signal to run at Vz the rate of the on-chip clock circuits. Preferably the clock doubler will allow instruction commands to be accepted on each external clock edge, but circuit modifications would allow external commands to be accepted on only one edge of the external clock, while internal functionality and input/output data would "burst" at double the external clock rate. The internally controlled clock high time eliminates the performance problems associated with the high duty cycles of some external clock signals. The clock doubler reduces the test times and allows testing at the highest rated clock speeds of a device on low speed and low cost production testers. Moreover, while the clock doubler is to be used primarily in a test mode, it can provide system designers with the ability to clock commands and data on each transition of the external clock. As noted, the clock high time is a function of /CAS latency which allows internal circuit optimization for supported /CAS latencies. The external clock signal should be reasonably symmetrical when using the clock doubler mode in order to generate a stable double rate clock signal internally. However, when in normal mode, the programmable clock modification circuitry compensates for large variations in duty cycle. In one embodiment, a one-shot is used with a look-ahead technique (a feed forward technique) which employs the leading edge of the external clock signal, uses the external clock signal, adds a time delay, and turns off the original external clock signal (internally) so that the trailing edge of the internally generated clock signal is governed by the internal circuitry. This approach generates one-shot pulses for normal

Clock-doubler With Delay Line Crack Activation [32

For normal operation and the clock high time for doubler mode is less than a quarter of the highest external clock period to be used in test mode. the present invention allows optimum design of the on-chip circuitry for each CAS latency and eliminates problems associated when either high or low duty cycles external clock timing signals are used. CAS latency changes are made via a conventional Mode Register included normally in the SDRAM. the clock doubler is preferably enabled or disabled via the special register normally included in the SDRAM. the new timing conditions are valid on the cycle following the mode register load instruction or the special register load instruction. Hence, the new clock mode is instantaneous and available on the next possible instruction cycle in the preferred embodiment. the preferred embodiment uses separately enabled one-shot timer circuits which produce pulses (HTLME and LT ME) in the Clock Doubler Test Mode with leading edges separated in time from one another. These are applied to a "clock selector" circuit which receives a signal (CLKBP) closely related to the externally supplied clock signal (CLKPAD), and produces a composite or derived signal (DCLKB) taking into consideration the one-shot timing signal or signals. CLKBP a signal CLKPAD externally supplied clock signal DCLKB composite or derived signal a node is coupled selectively to a power supply voltage VCC via at least first or second pull-up paths, and that node also is coupled selectively to VSS via at least first and second pull-down paths. DCLKB derived clock signal the one shot timer circuits include circuit elements which modify the duration of the generated timing pulse, based on a user-programmable status signal or mode. Figures 1A-1E collectively form a simplified block of various circuit elements of clock doubler circuitry according to the present invention Fig. 2 is a sketch of several waveforms useful for understanding the operation of the described embodiment in the Clock Doubler Test Mode; Fig. 3 is a sketch of several waveforms useful for understanding the described embodiment in the normal mode (not the test mode); Fig. 4 shows the clock mode circuit of the Fig. 1 embodiment Fig. 5 shows the clock pad buffer circuit of the Fig. 1 embodiment Fig. 6 shows the clock control circuit of the Fig. 1 embodiment Fig. 7 shows the clock selector circuit of the Fig. 1 embodiment Fig. 8 shows the clock selector circuit of the Fig. 1 embodiment the first sheet of drawings presents a simplified block diagram of clock generator, including the clock doubler circuitry, according to various aspects of the present invention. It will be understood that all of the circuits are constructed on a single chip as part of SDRAM

Clock-doubler With Delay Line For Windows (April-2025)

At least one, and preferably two, timers, e.g. one-shot circuits. a clock doubler circuit is incorporated as part of the circuit and method. This clock doubler allows the external clock signal to run at Vz the rate of the on-chip clock circuits. the clock doubler will allow instruction commands to be accepted on each external clock edge, but circuit modifications would allow external commands to be accepted on only one edge of the external clock, while internal functionality and input/output data would "burst" at double the external clock rate. the internally controlled clock high time eliminates the performance problems associated with the high duty cycles of some external clock signals. the clock doubler reduces the test times and allows testing at the highest rated clock speeds of a device on low speed and low cost production testers. the clock doubler is to be used primarily in a test mode, it can provide system designers with the ability to clock commands and data on each transition of the external clock. the clock high time is a function of /CAS latency which allows internal circuit optimization for supported /CAS latencies. the external clock signal should be reasonably symmetrical when using the clock doubler mode in order to generate a stable double rate clock signal internally. the programmable clock modification circuitry compensates for large variations in duty cycle. a one-shot is used with a look-ahead technique (a feed forward technique) which employs the leading edge of the external clock signal, uses the external clock signal, adds a time delay, and turns off the original external clock signal (internally) so that the trailing edge of the internally generated clock signal is governed by the internal circuitry. a look-ahead technique a feed forward technique This approach generates one-shot pulses for normal applications. the preferred embodiment uses two one-shots, again with a look-ahead technique. Accordingly, the present invention removes skew problems associated with clock modifications. More specifically, in an embodiment of the present invention, programmable one- shots vary the high time of an internal master clock for an SDRAM. the low-to-high transition of the external clock signal triggers (directly or indirectly) a one- shot. the time duration of this one-shot is dependent on the /CAS latency that is programmed into a mode register of the SDRAM. two programmable pulse widths are available, one width for a /CAS latency of 1, and a second width for CAS latencies of 2 and 3. Individual pulse widths for the allowed latencies are within the scope of this invention. the one-shot timing is selected such that preferably the clock high time for each latency is always less than one-half of the shortest external clock period associated with the programmed latency. Download Clock-doubler with delay line - Clock-doubler circuit simulation built in Java . Clock-doubler with delay line DOWNLOAD NOW 511 downloads so far.

EDN Access Delay line implements clock doubler

So that the capacitors 282 charge faster and the voltage on line 275 changes more quickly. It may be noted that the low time enable signal LTEN is kept high when the circuitry is not in the clock doubler test mode. With LTEN high, transistor 290 is kept off. Accordingly, the low riming signal LTTME, which is provided to the clock selector circuitry, is used only when the clock doubler mode is enabled. The invention addresses the problem of duty cycles different than 50% in the external clock signal by modifying the internal clock high time, using a precision delay time which is triggered by the rising edge of the external clock. Furthermore, the high pulse generated, under "normal operation" (non-doubler mode), modifies the pulse width differently for different /CAS latencies (our implementation programs the same pulse duration for /CAS latencies of 2 and 3, but changes the pulse duration for /CAS latency of 1. The invention includes programming different internal pulse widths for all possible /CAS latencies. If the mode register signal CLl is high, then the voltage at the gate electrode of transistor 272 will be low, and that transistor will be nonconductive. Accordingly, all of the resistances between transistor 276 and 280 will be in the circuit, and none of them will be shorted out by transistor 272. Accordingly, this larger resistance means that the current will be lower to line 275. This means that it will take longer to charge the capacitances 282. Accordingly, longer time is needed for the voltage at the input of inverter 284 to rise. Consequently, the output of this circuit, which is the timing signal HTTME, will be a longer pulse when CLl is high. On the other hand, if CLl is low, this is inverted by inverter 270, and transistor 272 is conductive. The source-drain path thereof shorts out much of the resistance between transistors 276 and 280. Consequently, the current through the constant current source is higher and the time needed to charge capacitors 282 is less. Accordingly, the output pulse HTIME is shorter in duration. The generation of the other timing signal LTTME is similar, but it is not modified on the basis of the status of the CLl signal. However, in a variation of the preferred embodiment, a similar change in the current can be achieved by adding a transistor and/or further resistances between transistors 292 and 295. Having described these circuits, it is useful to return to Figs. 2 and 3 to correlate some of the waveforms to the operation of various transistors and other circuit elements described in Fig. 7, the clock selector circuit 18. Fig. 7, it will be recalled, shows the circuitry leading

Official Version To Macos 10.12 Clock-Doubler With Delay Line

Applications. For testing applications (clock doubler test mode), the preferred embodiment uses two one-shots, again with a look-ahead technique. Accordingly, the present invention removes skew problems associated with clock modifications. More specifically, in an embodiment of the present invention, programmable one- shots vary the high time of an internal master clock for an SDRAM. For normal operation, the low-to-high transition of the external clock signal triggers (directly or indirectly) a one- shot. The time duration of this one-shot is dependent on the /CAS latency that is programmed into a mode register of the SDRAM. Preferably, two programmable pulse widths are available, one width for a /CAS latency of 1, and a second width for CAS latencies of 2 and 3. Individual pulse widths for the allowed latencies are within the scope of this invention. The one-shot timing is selected such that preferably the clock high time for each latency is always less than one-half of the shortest external clock period associated with the programmed latency for normal operation and the clock high time for doubler mode is less than a quarter of the highest external clock period to be used in test mode. By determining the clock high time internally, independent of the external clock high duration, the present invention allows optimum design of the on-chip circuitry for each CAS latency and eliminates problems associated when either high or low duty cycles external clock timing signals are used. Preferably, CAS latency changes are made via a conventional Mode Register included normally in the SDRAM. The clock doubler is preferably enabled or disabled via the special register normally included in the SDRAM. Preferably, the new timing conditions are valid on the cycle following the mode register load instruction or the special register load instruction. Hence, the new clock mode is instantaneous and available on the next possible instruction cycle in the preferred embodiment. More specifically, the preferred embodiment uses separately enabled one-shot timer circuits which produce pulses (HTLME and LT ME) in the Clock Doubler Test Mode with leading edges separated in time from one another. These are applied to a "clock selector" circuit which receives a signal (CLKBP) closely related to the externally supplied clock signal (CLKPAD), and produces a composite or derived signal (DCLKB) taking into consideration the one-shot timing signal or signals. In the preferred embodiment of the clock selector circuit, a node is coupled selectively to a power supply voltage VCC via at least first or second pull-up paths, and that node also is coupled selectively to VSS via at least first and second pull-down paths. These paths operate to govern the signal level of the derived clock signal (DCLKB) which can be used as an output. Download Clock-doubler with delay line - Clock-doubler circuit simulation built in Java . Clock-doubler with delay line DOWNLOAD NOW 511 downloads so far.

Clock-doubler With Delay Line Crack Free License Key

Circuitry, and are integrated on the same circuit containing the SDRAM circuitry. Accordingly, while the first sheet of drawings may appear to be several distinct devices, they preferably are interconnected elements of clock circuitry fabricated on a single integrated circuit device. the preferred circuits of Figs. 1A-1E each have three power supply connections for VCC, VSS, and VBB. Many signal names or terms appear in Figs. 1A-1E and throughout the following description. Accordingly, it may be useful to set forth in the following Table 1 a listing of them, in alphabetic order. Fig. 1A shows a clock mode circuit 12 to receive a CL1 signal generally but not necessarily from a Mode Register (not illustrated). the Mode Register is a storage capability or location on the SDRAM or other device from which the present clock modification circuits are controlled (enabled or disabled). Other means of providing the CLl signal may be used with the present invention. the CL1 signal has a logic value of 1 when a CAS latency of 1 is selected. CAS latency generally connotes the time between an instruction and the ensuing output data. Thus, where CAS latency is set to 1, output data will become valid one cycle after the read command. CAS latency of 2 means the data will become valid two cycles after the read command. Another input signal to clock mode circuit 12 is a clock doubler test mode signal (CDTM) which is generally but not necessarily provided from a Test Register or special register on the SDRAM. Illustratively, CDTM equals 1 when the clock doubler test mode is enabled. the output of circuit 12 is a clock timing modification signal CLKTMB, which equals zero when the clock circuitry is in the clock doubler test mode. the preferred embodiment of the invention uses a clock mode circuit which determines whether the clock doubler mode is to occur. This circuit could be omitted or another circuit could be substituted for it. a signal from a RAM register or elsewhere could indicate this mode. Fig. IB represents a clock pad buffer circuit 14, the main function of which is to receive the externally supplied clock signal CLKPAD and provide a buffered signal based thereon. Other functions are also performed in the preferred circuit such as generating master clock signals from a derived clock signal DCLKB, and performing some logic functions. another input to circuit 14 is a clock active signal CLKONB, provided from another part of the clock circuitry, which is normally low but goes high when the chip is in a power-down mode. An enabling signal ENCLKB is inputted from other parts of the clock circuitry and goes low whenever the two master clock